
		AT&T Laboratories Cambridge

Collapsed LAN

These pages were last modified 28/11/01.

The MarkI PCI-Link NIC

The above image (when enlarged) shows the functional blocks of the MarkI network card. The network card is built around the concept of serialising an i960-style local bus from a V3 PCI bus bridge using HP's G-Link chipset and optical fibre transceivers. The latter convert a 23-bit parallel data stream at 62 MHz to a serial data stream at approximately 1.5Gbit/s. It should be noted that other physical layers are possible and desirable, especially given a requirement for commodity high performance switching. However, the G-Link maps neatly onto our target 33 MHz, 32-bit PCI bus, and was relatively straightforward to interface to.

The main requirement of our design was thus to convert and multiplex the 43 bit local bus (32-bit data + byte enable + parity + control signals) at around 30 MHz to a 23-bit protocol suitable for the G-Link at 60 MHz. This protocol is able to support read and write burst transactions with flow control.

The MarkI board suffered from a particular pipeline problem resulting in 54 MHz operation and a stall on each network transaction. However, it was able to achieve raw data transfer rates in excess of 800Mbps, and small user level to user level application write transfer latencies of 1-2us.

Please note that the techniques disclosed here have been the subject of patent applications